Senior RFIC Design Engineer, Sophia Antipolis (France) or Reading (UK)
SOPHIA ANTIPOLIS, FRANCE or READING (UK)
We are searching for a Senior level radio frequency integrated circuit (RFIC) design engineer to join a strong group of RFIC designers to help lead us in the development of RF transceivers to address the LTE 5G markets. Working within a dynamic design team you will participate in the development of next generation RFIC products for 5G wireless communication networks.
Responsibilities:
- Specify, design and verify key circuits and sub-systems of integrated RF transceivers
- Work closely with other teams to facilitate the design and production process,e.g. Software, Signal Processing, Product Integration, Sales & Marketing
- Provide broad technical expertise and mentor junior engineers within the team
Profile:
- Highly motivated, pro-active self-starter
- Strong sense of ownership and responsibility
- Creative thinker with strong problem solving skills
- Team oriented attitude
- Ability to thrive in a multicultural environment
- Ability to communicate well with cross-functional teams
- Excellent written and oral communications skills
Required experience:
- Engineering degree in a relevant discipline. BSc, MSc or equivalent
- 5 to 10 years experience of relevant IC development
- Fluent English speaker
- Recent successful RFIC project contributions on highly integrated RF transceivers, ideally related to broadband wireless communication systems, e.g. WiFi or LTE, on a nano-metre scale RF-CMOS technology
- Understanding of Low power / low noise design techniques for Analogue and RF
- Knowledge of Design for Manufacture considerations on cutting edge processes
- Full appreciation of RF and baseband layout techniques
Required detailed knowledge at system level:
- RFIC System and architecture design, ideally for OFDM applications
- RFIC Sub-system and block level definition & specification
- System simulation
Additional useful experience may include:
- Integrated single chip RF + Digital baseband projects
- Top level chip simulation and functional verification
- Analogue behavioral language modeling (e.g. Verilog-AMS)
- Mixed-mode simulation environments (e.g. mixed verilog and device level )
- Direct conversion Rx and Tx architectures and associated considerations
- DFT and BIST for Analogue and RF circuits
- Silicon test and de-bugging
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