DFT/Synthesis Design Principal Engineer – Paris, France

Paris – France

Required Experience:

  • Engineering degree in a relevant discipline. BSc, MSc or equivalent
  • Minimum of 10 years experience of ASIC development.
  • Good experience of Verilog/VHDL
  • Good knowledge of synthesis, static timing analysis and DFT insertion tools
  • Good knowledge of P&R tools would be a bonus

Profile:

  • Highly motivated, pro-active self-starter
  • Strong sense of ownership and responsibility
  • Creative thinker with strong problem solving skills
  • Team oriented attitude and ability to thrive in a multicultural environment
  • Excellent written and oral communications skills

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