ASIC Layout Engineer – Singapore


You will be responsible for the physical implementation of Sequans next generation chipsets (5G and 4G), from synthesis netlist to GDSII, for power and area optimized chips in advanced nodes (12 nm, 22 nm). You will also be responsible for the physical verification of the chip.

Good communication is required to exchange information with Front-End team based in Paris.

Required Experience:

  • At least 4 years of experience in place and route
  • Experience in DRC, LVS and IR drop analysis
  • Knowledge of Cadence tools would be a bonus
  • Experience of chips with power gating would be a bonus
  • Experience of 12nm/22nm process would be a bonus


  • Fast learning capabilities, highly motivated, self-starter, autonomous
  • Interested in challenges of new technologies and novel algorithms
  • Ability to work in a fast moving and multicultural environment
  • Team player, commitment & customer focus
  • Excellent written and oral communications skills, fluent English


Certified by Operators Worldwide