ASIC Design Engineer — Colombes or Sophia Antipolis, France

  • 0
  • July 24, 2018

RESPONSIBILITIES:

  • Specify, design and validate different modules linked to the MAC and PHY layers of LTE standards and to CPU platform peripherals and interfaces.
  • Work closely with other teams to facilitate the design and production process,
    e.g. Software, Signal Processing, Product Integration.

 

PROFILE:

  • Highly motivated, pro-active self-starter
  • Strong sense of ownership and responsibility
  • Creative thinker with strong problem solving skills
  • Team oriented attitude
  • Ability to thrive in a multicultural environment
  • Ability to communicate well with cross-functional teams
  • Excellent written and oral communications skills
  • Fluent written and spoken English

 

REQUIRED EXPERIENCE:

  • Engineering degree in a relevant discipline. BSc, MSc or equivalent
  • Minimum of 3 years’ experience of ASIC and/or FPGA development
  • Good experience of Verilog/VHDL
  • Knowledge of synthesis and static timing analysis tools would be a bonus
  • Experience of implementing signal processing modules in RTL would be a bonus

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